Drain-extended (DE) architectures have been used to provide transistors having higher breakdown voltages (BV) for use in high power and high voltage applications. Briefly, in a DE transistor the drain is extended by a low doped semiconductor region which depletes during reverse biasing, thereby allowing much of voltage to be dropped across a channel in the substrate, and thereby reducing the electric field across a gate oxide to a safe level.
An example of a conventional drain-extended n-channel MOS transistor 100 is depicted in FIG. 1.
Referring to FIG. 1, the transistor 100 generally includes a source 102 and drain 104 formed in a p-type semiconductor substrate 106 (p-substrate), and separated by a channel 108 underlying a gate electrode 110. Generally, the transistor 100 further includes an isolation structure 112, such as a field oxidation region (as shown) or a shallow trench isolation (STI), formed at least partially under the gate electrode 110 and isolating the drain 104 from the channel 108 to increase the BV between the source 102 and drain 104. A first well 114 (which is doped to be p-type for a p-channel transistor and n-type for an n-channel transistor) encompasses the drain 104 forms a drain extension region 116. A second well 118, shown here as p-body or p-well, is implanted within the first well 114 to encompass the source 102. Thus, the BV of the transistor 100 is defined by a junction or diode (D1) between the first and second wells, plus a distance or length (L1) of the isolation structure 112 separating the drain 104 from the drain extension region.
Examples of other conventional drain-extended transistor including a reduced surface effect (RESURF) architecture are shown in FIGS. 2 and 3. In particular, a DE NMOS transistor 200 having a RESURF architecture is depicted in FIG. 2, a DE PMOS is shown in FIG. 3. This architecture has been published to achieve higher BV. The basic idea is to extend the drain by a low doped semiconductor region which depletes during reverse biasing and inverts during forward biasing.
Referring to FIG. 2, a DE NMOS transistor 200 generally includes a n+ doped source 202 and n+ doped drain 204 formed in a p-substrate 206, and separated by a channel 208 underlying a gate electrode 210. Generally, the transistor 200 further includes an isolation structure 212, such as a field oxidation region or a STI (as shown) isolating the drain 204 from the channel 208 to increase the BV between the source 202 and drain 204. A first n-type well 214 encompasses the drain 204 forms a drain extension region 216. A second p-well or p-body 218 is implanted in the substrate 206 encompassing the source 202 and overlapping the first well 214. As noted above, the drain extension region 216 is lightly doped to deplete during reverse biasing providing a high resistance increasing the BV of the transistor 200. Thus, the BV of the transistor 200 is defined by the doping and the length of the drain extension region 216 separating the drain 204 from the channel region 208.
Referring to FIG. 3, a DE PMOS transistor 300 includes a p+ doped source 302 and drain 304 formed in a p-substrate 306, and separated by a channel 308 underlying a gate electrode 310. The transistor 300 further includes an isolation structure 312, such as a STI, isolating the drain 304 from the channel 308. An n-type first well 314 encompasses the source 302. A second p-well 316 is implanted in the first well 314 encompasses the drain 304 and the isolation structure 312, forming a drain extension region 318. The drain extension region 318 is lightly doped to deplete during reverse biasing providing a high resistance increasing the BV of the transistor 300.
Although the DE transistors described above do provide higher breakdown voltages than conventional transistors, they suffer from a number of problems or shortcomings.
One problem is conventional methods of fabricating DE transistors require separate device wells and doping levels, which are typically not compatible with complimentary metal-oxide-semiconductor (CMOS) processes commonly used in manufacturing integrated circuits (ICs). Moreover, even when the methods of fabricating DE transistors are compatible with the manufacturing processes, the additional masking and implant steps required render them not cost effective.
Accordingly, there is a need for drain-extended high voltage transistor having architecture compatible with conventional methods of fabricating CMOS circuits. It is further desirable that the fabrication methods for making the DE transistor are capable of being fully integrated with or embedded into an existing CMOS flow with only minimal additional masking and process steps, and therefore are cost effective.
The present invention provides a solution to these and other problems, and offers further advantages over conventional methods of fabricating high voltage, DE transistors.